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EL8176
Data Sheet April 3, 2009 FN7436.8
Micropower Single Supply Rail-to-Rail Input-Output Precision Op Amp
The EL8176 is a precision low power, operational amplifier. The device is optimized for single supply operation between 2.4V to 5.5V. The EL8176 draws minimal supply current while meeting excellent DC-accuracy noise and output drive specifications. Competing devices seriously degrade these parameters to achieve micropower supply current. The EL8176 can be operated from one lithium cell or two Ni-Cd batteries. The input range includes both positive and negative rail. The output swings to both rails.
Features
* 55A supply current * 100V max offset voltage (8 Ld SO) * 2nA input bias current * 400kHz gain-bandwidth product * Single supply operation down to 2.4V * Rail-to-rail input and output * Output sources 31mA and sinks 26mA load current * Pb-free plus (RoHS compliant)
Applications
* Battery- or solar-powered systems * 4mA to 20mA current loops * Handheld consumer products * Medical devices
Ordering Information
PART NUMBER EL8176FWZ-T7* (Note 1) PART MARKING BBVA PACKAGE (Pb-Free) 6 Ld SOT-23 6 Ld SOT-23 8 Ld SO 8 Ld SO 6 Ld WLCSP (1.5mmx1.0mm) PKG. DWG. # MDP0038 MDP0038 MDP0027 MDP0027 W3x2.6C
EL8176FWZ-T7A* BBVA (Note 1) EL8176FSZ (Note 1) EL8176FSZ-T7* (Note 1) EL8176FIZ-T7* (Note 2) 8176FSZ 8176FSZ 176Z
* Thermocouple amplifiers * Photodiode pre amps * pH probe amplifiers
*Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. These Intersil Pb-free WLCSP and BGA packaged products products employ special Pb-free material sets; molding compounds/die attach materials and SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2006, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL8176 Pinouts
EL8176 (6 LD SOT-23) TOP VIEW
OUT 1 V- 2 IN+ 3 6 V+ 5 EN 4 INNC 1 IN- 2 IN+ 3 V- 4 +
EL8176 (8 LD SO) TOP VIEW
8 EN 7 V+ A 6 OUT 5 NC B
EL8176 (6 LD WLCSP) TOP VIEW
1 2
+-
DNC*
OUT
V+
V-
C
IN-
IN+
*DO NOT CONNECT
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FN7436.8 April 3, 2009
EL8176
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (VS) and Pwr-up Ramp Rate . . . . . . . 5.75V, 1V/s Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Current into IN+, IN-, and EN. . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V ESD Tolerance Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 230 6 Ld WLCSP Package . . . . . . . . . . . . . . . . . . . . . . . 130 8 Ld SO Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Ambient Operating Temperature Range . . . . . . . . -40C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . -65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, VEN = 0V, TA = +25C unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C. Temperature data established by characterization. DESCRIPTION CONDITIONS MIN (Note 4) TYP MAX (Note 4) UNIT
PARAMETER DC SPECIFICATIONS VOS
Input Offset Voltage
8 Ld SO
-100 -220
25
100 220
V V V V V V/Mo V/C
6 Ld SOT-23
-350 -350
80
350 350
WLCSP V OS -----------------Time V OS --------------T IOS Long Term Input Offset Voltage Stability Input Offset Drift vs Temperature Input Offset Current
-500
-75 2.4 0.7
500
-1 -4
0.4
1 4
nA nA nA nA V dB dB
IB
Input Bias Current
-2 -5
0.5
2 5 5
CMIR CMRR
Input Voltage Range Common-Mode Rejection Ratio
Guaranteed by CMRR test VCM = 0V to 5V
0 90 90 110
PSRR
Power Supply Rejection Ratio
VS = 2.4V to 5.5V
90 90
110
dB dB
AVOL
Large Signal Voltage Gain
VO = 0.5V to 4.5V, RL = 100k
200 200
500
V/mV V/mV
VO = 0.5V to 4.5V, RL = 1k
25
V/mV
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FN7436.8 April 3, 2009
EL8176
Electrical Specifications
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, VEN = 0V, TA = +25C unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C. Temperature data established by characterization. (Continued) DESCRIPTION Maximum Output Voltage Swing SOT-23/SO-8 CONDITIONS VOL; Output low, RL = 100k MIN (Note 4) TYP 3 MAX (Note 4) 8 10 VOL; Output low, RL = 1k 130 200 300 VOH; Output high, RL = 100k 4.994 4.992 VOH; Output high, RL = 1k 4.750 4.7 Maximum Output Voltage Swing WLCSP VOL; Output low, RL = 100k 3 8 10 VOL; Output low, RL = 1k 130 200 300 VOH; Output high, RL = 100k VOH; Output high, RL = 1k 4.991 4.750 4.7 IS,ON Supply Current, Enabled VEN = 5V, SOT-23/SO-8 35 30 VEN = 5V, WLCSP 60 55 IS,OFF Supply Current, Disabled VEN = 0V, SOT-23/SO-8 only 3 85 55 75 90 110 120 10 10 IO+ Short Circuit Output Sourcing Current RL = 10 18 18 IOShort Circuit Output Sinking Current RL = 10 17 15 VS Supply Voltage Guaranteed by PSRR test 2.4 2.4 VINH VINL IENH Enable Pin High Level Enable Pin Low Level Enable Pin Input Current SOT-23 and SO packages only SOT-23 and SO packages only VEN = 5V, SOT-23 and SO packages only VEN = 0V, SOT-23 and SO packages only 0.25 0.7 2 0.8 2.0 2.5 -0.5 -1 0 +0.5 +1 5.5 5.5 26 31 4.997 4.867 4.867 4.997 UNIT mV mV mV mV V V V V mV mV mV mV V V V A A A A A A mA mA mA mA V V V V A A A A
PARAMETER VOUT
IENL
Enable Pin Input Current
AC SPECIFICATIONS GBW Unity Gain Bandwidth Gain Bandwidth Product -3dB Bandwidth AV = 100, RF = 100k, RL = 10k, RG = 1k to VCM AV = 1, RF = 0, RL = 100k to VCM, VOUT = 10mVP-P 400 1 kHz MHz
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FN7436.8 April 3, 2009
EL8176
Electrical Specifications
V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, VEN = 0V, TA = +25C unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C. Temperature data established by characterization. (Continued) DESCRIPTION Input Noise Voltage Peak-to-Peak Input Noise Voltage Density iN ISO CMRR PSRR+ PSRRInput Noise Current Density Off-State Input to Output Isolation Input Common Mode Rejection Ratio Power Supply Rejection Ratio (V+) Power Supply Rejection Ratio (V-) CONDITIONS f = 0.1Hz to 10Hz, RL = 10k to VCM fO = 1kHz fO = 1kHz VEN = 5V, fO = 1kHz, AV = +1, VIN = 1VP-P SOT-23 and SO packages only fO = 120Hz; VCM = 1VP-P, fO = 120Hz; V+, V- = 2.5V, VSOURCE = 1VP-P fO = 120Hz; V+, V- = 2.5V, VSOURCE = 1VP-P MIN (Note 4) TYP 1.5 28 0.16 -73 -70 -90 -70 MAX (Note 4) UNIT VP-P nV/Hz pA/Hz dB dB dB dB
PARAMETER eN
TRANSIENT RESPONSE SR tr, tf, Large Signal Slew Rate Rise Time, 10% to 90%, VOUT Fall Time, 90% to 10%, VOUT tr, tf, Small Signal Rise Time, 10% to 90%, VOUT Fall Time, 90% to 10%, VOUT tEN AV = +2, VOUT = 2VP-P, Rg = Rf = RL = 10k to VCM AV = +2, VOUT = 2VP-P, Rg = Rf = RL = 10k to VCM AV = +2, VOUT = 10mVP-P, Rg = Rf = RL = 10k to VCM AV = +2, VOUT = 10mVP-P, Rg = Rf = RL = 10k to VCM
0.065 0.13 0.3
V/s s s s s s s
18 19 2.4 2.4 4 0.1
Enable to Output Turn-on Delay Time, 10% VEN = 5V to 0V, AV = +2, EN to 10% VOUT (SOT-23, SO packages) Rg = Rf = RL = 10k to VCM Enable to Output Turn-off Delay Time, 10% VEN = 0V to 5V, AV = +2, EN to 10% VOUT (SOT-23, SO packages) Rg = Rf = RL = 10k to VCM
NOTE: 4. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
Typical Performance Curves
100 80 PHASE 60 GAIN (dB) 40 0 20 0 -20 10 GAIN -50 -40 -100 -150 1M -80 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) -120 10M -80 200 150 80 100 PHASE () 50 40 0 PHASE () GAIN (dB) 40 120 80
0
-40
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 1. AVOL vs FREQUENCY @ 1k LOAD
FIGURE 2. AVOL vs FREQUENCY @ 100k LOAD
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FN7436.8 April 3, 2009
EL8176 Typical Performance Curves
1 NORMALIZED GAIN (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 V+ = 5V RL = 10k CL = 8.3pF AV = +2 VOUT = 10mVP-P 1k Rf = Rg = 100k Rf = Rg = 10k NORMALIZED GAIN (dB)
(Continued)
3 2 1 0 -1 -2 -3 -4 -5 V+ = 5V RL = 1k -6 CL = 8.3pF -7 A = +1 V -8 10 100 VOUT = 10mV VOUT = 50mV VOUT = 100mV VOUT = 1V
Rf = Rg = 1k 10k FREQUENCY (Hz) 100k 1M
-9 100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 3. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES Rf/Rg
FIGURE 4. GAIN vs FREQUENCY vs VOUT, RL = 1k
3 2 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 0 -1 -2 -3 -4 -5 -6 -7 V+ = 5V RL = 10k CL = 8.3pF AV = +1 100 VOUT = 10mV VOUT = 50mV VOUT = 100mV VOUT = 1V
3 2 1 0 -1 -2 -3 -4 -5 -6 -7 1k 10k 100k 1M 10M V+ = 5V RL = 100k CL = 8.3pF AV = +1 100 VOUT = 10mV VOUT = 50mV VOUT = 100mV VOUT = 1V
-8 10
-8 10
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. GAIN vs FREQUENCY vs VOUT, RL = 10k
FIGURE 6. GAIN vs FREQUENCY vs VOUT, RL = 100k
3 2 NORMALIZED GAIN (dB) 1 0 -2 -3 -4 -5 -6 -7 -8 10 V+ = 5V CL = 8.3pF AV = +1 VOUT = 10mVP-P 100 1k 10k 100k 1M 10M RL = 100k RL = 1k GAIN (dB) -1 RL = 10k
70 60 50 40 30 20 10 0 -10 10 AV = 10 AV = 10, Rg = 1k, Rf = 9.09k AV = 1 AV = 1, Rg = INF, Rf = 0 100 1k 10k 100k FREQUENCY (Hz) 1M 10M AV = 101 AV = 1001 AV = 1001, Rg = 1k, Rf = 1M AV = 101, Rg = 1k, Rf = 100k V+ = 5V CL = 8.3pF RL = 10k VOUT = 10mVP-P
FREQUENCY (Hz)
FIGURE 7. GAIN vs FREQUENCY vs RL
FIGURE 8. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
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FN7436.8 April 3, 2009
EL8176 Typical Performance Curves
2 1 0 -1 GAIN (dB) -3 -4 -5 -6 -7 -8 -9 1k RL = 10k CL = 8.3pF AV = +1 VOUT = 10mVP-P 10k V+ = 5V GAIN (dB) -2 35 30 25 20 15 V+ = 2V 10 5 100k FREQUENCY (Hz) 1M 10M RL = 10k CL = 8.3pF AV = 100 VOUT = 10mVP-P RF = 221k RG = 2.23k 1k V+ = 5V V+ = 2.5V
(Continued)
45 40 V+ = 2.5V
V+ = 2V
0 100
10k FREQUENCY (Hz)
100k
1M
FIGURE 9. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FIGURE 10. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
6 5 4 3 2 1 0 -1 -2 -3 -4 V = 5V + -5 R = 10k L -6 AV = +1 -7 VOUT = 10mVP-P -8 -9 1k 10k
20 CL = 64.3pF CL = 47.3pF CL = 35.3pF CMRR (dB) 0 -20 -40 -60 -80 -100 -120 100k FREQUENCY (Hz) 1M 10M V+ = 5V RL = OPEN CL = 8.3pF AV = +1 VCM = 1VP-P 1 10 100 1k 10k 100k 1M
NORMALIZED GAIN (dB)
CL = 26.3pF CL = 8.3pF
FREQUENCY (Hz)
FIGURE 11. GAIN vs FREQUENCY vs CL
FIGURE 12. CMRR vs FREQUENCY; V+, V- = 2.5V
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 1
0 V+ = 5V RL = OPEN CL = 8.3pF AV = +1 VCM = 1VP-P -10 OFF ISOLATION (dB) -20 -30 -40 -50 -60 -70 -80 -90 10 100 1k 10k 100k 1M -100 1 10 100 1k 10k 100k 1M 10M V+ = 5V RL = OPEN CL = 8.3pF AV = +1 VIN = 1VP-P
PSRR-
PSRR (dB )
PSRR+
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. PSRR vs FREQUENCY, V+, V- = 2.5V
FIGURE 14. OFF ISOLATION vs FREQUENCY; V+, V- = 2.5V
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FN7436.8 April 3, 2009
EL8176 Typical Performance Curves
1000 V+ = 5V RL = OPEN CL = 8.3pF AV = +1 100 INPUT CURRENT NOISE (pAHz) INPUT VOLTAGE NOISE (nVHz)
(Continued)
10 V+ = 5V RL = OPEN CL = 8.3pF AV = +1 1
10 0.1
1
10 100 1k FREQUENCY (Hz)
10k
0.1 0.1
1
10 100 1k FREQUENCY (Hz)
10k
FIGURE 15. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY
FIGURE 16. INPUT CURRENT NOISE DENSITY vs FREQUENCY
2.0
2.5 2.0 1.5 LARGE SIGNAL (V) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 1 2 3 4 5 6 TIME (s) 7 8 9 10 -2.5 0 50 100 150 200 250 TIME (s) 300 350 400 V+, V- = 2.5V RL = 10k CL = 8.3pF Rg = 10k Rf = 30k AV = 4 VOUT = 4VP-P
INPUT NOISE (V)
V+ = 5V 1.5 RL = OPEN CL = 8.3pF 1.0 Rg = 10, Rf = 10k AV = 1000 0.5 0 -0.5 -1.0 -1.5 -2.0 0
FIGURE 17. INPUT VOLTAGE NOISE 0.1Hz TO 10Hz
FIGURE 18. LARGE SIGNAL STEP RESPONSE
12 10 SMALL SIGNAL (mV) 8 V-ENABLE (V) 6 4 2 0 -2 0 50 100 150 200 250 TIME (s) 300 350 400 V+, V- = 2.5V RL = 10k CL = 8.3pF Rg = Rf = 10k AV = 2 VOUT = 10mVP-P
3.0 VENABLE 2.5 VOUT 2.0 1.5 1.0 0.5 0 -0.5 0 20 40 60 80 100 120 TIME (s) 140 160 180 V+, V- = 2.5V Rg = Rf = RL = 10k CL = 8.3pF AV = +2 VOUT = 2VP-P
3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 200 OUTPUT (V)
FIGURE 19. SMALL SIGNAL STEP RESPONSE
FIGURE 20. ENABLE TO OUTPUT RESPONSE
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FN7436.8 April 3, 2009
EL8176 Typical Performance Curves
100 80 60 40 V+, V- = 2.5V Rg = 100 Rf = 10k RL = INF CL = 8.3pF AV = +11 VOUT = 2VP-P 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCM (V) IBIAS (A) VIO (V) 20 0 -20 -40 -60 -80 -100 -0.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCM (V)
(Continued)
2.0 1.5 V+, V- = 2.5V Rg = 100 Rf = 10k RL = INF CL = 8.3pF AV = +11 VOUT = 2VP-P
FIGURE 21. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
FIGURE 22. INPUT OFFSET CURRENT vs COMMON-MODE INPUT VOLTAGE
200 INPUT OFFSET VOLTAGE (V) 150 100 50 0 -50 -100 -150 -200 0 1 2 3 4 5 OUTPUT VOLTAGE (V) VDD = 2.5V VDD = 5V VCM = VDD/2 AV = -1 SUPPLY CURRENT (A)
60 50 40 30 20 10 0 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
FIGURE 23. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE
FIGURE 24. SUPPLY CURRENT vs SUPPLY VOLTAGE
75 n = 12 SUPPLY CURRENT (A) 70 65 MAX 60 MIN 55 MEDIAN 50 45 -40 SO, SOT-23 PACKAGE SUPPLY CURRENT (A)
100 n = 12 95 90 85 80 75 70 65 -20 0 20 40 60 80 100 120 60 -40 -20 0 20 40 MIN MAX
WLCSP
MEDIAN
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 25. SUPPLY CURRENT vs TEMPERATURE VS = 2.5V ENABLED. RL = INF
FIGURE 26. SUPPLY CURRENT vs TEMPERATURE VS = 2.5V ENABLED. RL = INF
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FN7436.8 April 3, 2009
EL8176 Typical Performance Curves
7 DISABLED SUPPLY CURRENT (A) 6 n = 12 CURRENT (nA) 5 4 3 2 MIN 1 0 -40 0 MIN -20 0 20 40 60 80 100 120 -0.5 -40 -20 0 20 40 60 80 100 120 MEDIAN MAX
(Continued)
2.5 n = 12 2.0 1.5 MAX 1.0 0.5
MEDIAN
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 27. DISABLED SUPPLY CURRENT vs TEMPERATURE VS = 2.5V RL= INF
FIGURE 28. IBIAS (+) vs TEMPERATURE VS = 2.5V
3.0 n = 12 2.5 2.0 1.5 1.0 0.5 0 -0.5 -40 MEDIAN MIN -20 0 20 40 60 80 100 120 MAX CURRENT (nA)
2.5 n = 12 2.0 1.5 1.0 MEDIAN 0.5 0 MIN -0.5 -40 -20 0 20 40 60 80 100 120 MAX
CURRENT (nA)
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 29. IBIAS (+) vs TEMPERATURE VS = 1.2V
FIGURE 30. IBIAS (-) vs TEMPERATURE VS = 2.5V
3.0 2.5 CURRENT (nA) 2.0 1.5 1.0 MEDIAN 0.5 0 -0.5 -40 MIN -20 0 20 40 60 80 100 120 MAX n = 12
2.5 n = 12 2.0 CURRENT (nA) 1.5 MAX 1.0 0.5 0 MIN -0.5 -40 -20 0 20 40 60 80 100 120
MEDIAN
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 31. IBIAS (-) vs TEMPERATURE VS = 1.2V
FIGURE 32. INPUT OFFSET CURRENT vs TEMPERATURE VS = 2.5V
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FN7436.8 April 3, 2009
EL8176 Typical Performance Curves
2.5 n = 12 2.0 CURRENT (nA) 1.5 1.0 0.5 MEDIAN 0 MIN -0.5 -40 -20 0 20 40 60 80 100 120 -50 -40 -20 0 20 40 60 80 100 120 0 MIN MAX VOS (V) 100 150 MAX MEDIAN 50
(Continued)
200 n = 12 SO PACKAGE
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 33. INPUT OFFSET CURRENT vs TEMPERATURE VS = 1.2V
FIGURE 34. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = 2.5V
200 n = 12 150 VOS (V) MAX MEDIAN 50
SO PACKAGE
400 n = 12 300 200 VOS (V) 100 MEDIAN 0 MAX SOT-23 PACKAGE
100
0 MIN -50 -40 -20 0 20 40 60 80 100 120
-100 MIN -200 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 35. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = 1.2V
FIGURE 36. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = 2.5V
200 150 100 VOS (V) 50 0 -50 -100 -150 -200 -40
n = 12 MAX
SOT-23 PACKAGE
150 n = 12 100 MAX 50 VOS (V) 0 50 MEDIAN WLCSP
MEDIAN
MIN
MIN 100 150 -40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 37. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = 1.2V
FIGURE 38. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = 2.5V
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FN7436.8 April 3, 2009
EL8176 Typical Performance Curves
150 n = 12 100 50 0 -50 MIN -100 -150 -40 100 95 -40 MEDIAN CMRR (dB) VOS (V) MAX WLCSP 120 115 110 105 MAX
(Continued)
125 n = 12
MEDIAN MIN
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 39. INPUT OFFSET VOLTAGE vs TEMPERATURE VS = 1.2V
FIGURE 40. CMRR vs TEMPERATURE VCM = +2.5V TO -2.5V
140 135 130 PSRR (dB) 125 120 115 110 105 100 95 -40
4.91 n = 12 4.90 4.89 MAX VOUT (V) 4.88 4.87 4.86
n = 12 MAX
MEDIAN
MEDIAN
MIN 4.85 4.84
MIN -20 0 20 40 60 80 100 120
4.83 4.82 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 41. PSRR vs TEMPERATURE VS = 1.2V TO 2.5V
FIGURE 42. POSITIVE VOUT vs TEMPERATURE RL = 1k VS = 2.5V
240 220 200 VOUT (mV)
n = 12
4.9982 4.9980 4.9978 MAX MEDIAN VOUT (V) 4.9976 4.9974 4.9972 4.9970 4.9968 4.9966 4.9964
n = 12 MAX
180 160 140
MEDIAN
MIN 120 100 80 -40 -20 0 20 40 60 80 100 120
MIN
4.9962 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 43. NEGATIVE VOUT vs TEMPERATURE RL = 1k VS = 2.5V
FIGURE 44. POSITIVE VOUT vs TEMPERATURE RL = 100k VS = 2.5V
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FN7436.8 April 3, 2009
EL8176 Typical Performance Curves
5.5 n = 12 5.0 SLEW RATE (V/s) 4.5 MAX 4.0 3.5 MEDIAN 3.0 2.5 -40 0.21 0.19 MAX 0.17 0.15 0.13 MIN 0.11 0.09 -40 MEDIAN
(Continued)
0.23 n = 12
VOUT (mV)
MIN
-20
0
20 40 60 80 TEMPERATURE (C)
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
FIGURE 45. NEGATIVE VOUT vs TEMPERATURE RL = 100k VS = 2.5V
FIGURE 46. +SLEW RATE vs TEMPERATURE VS = 2.5V INPUT = 0.75V, AV = 2
0.17 n = 12 0.16 CURRENT (pA) 0.15 AVOL (V/mV) 0.14 0.13 MIN 0.12 MEDIAN MAX
900 800 700 600 500 400 300 200
n = 12 MAX
MEDIAN
MIN
0.11 0.10 -40
100 -20 0 20 40 60 80 100 120 0 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 47. -SLEW RATE vs TEMPERATURE VS = 2.5V INPUT = 0.75V, AV = 2
FIGURE 48. AVOL, RL = 100k, VS 2.5V, VO = 2V
Pin Descriptions
SO PIN NUMBER 1, 5 2 3 4 4 3 2 C1 C2 B2 A1 6 7 8 1 6 5
V+
SOT-23 PIN 6 Ld WLCSP NUMBER PIN NUMBER
PIN NAME NC ININ+ VDNC OUT V+ EN
EQUIVALENT CIRCUIT No internal connection Circuit 1 Circuit 1 Circuit 4 Amplifier's inverting input
DESCRIPTION
Amplifier's non-inverting input Negative power supply Do not connect. Pin must be left floating.
A2 B1
Circuit 3 Circuit 4 Circuit 2
Amplifier's output Positive power supply Amplifier's enable pin with internal pull-down; Logic "1" selects the disabled state; Logic "0" selects the enabled state.
V+ OUT V+
CAPACITIVELY COUPLED ESD CLAMP
V+
EN ININ+ VVCIRCUIT 1 CIRCUIT 2 CIRCUIT 3
VVCIRCUIT 4
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FN7436.8 April 3, 2009
EL8176 Applications Information
Introduction
The EL8176 is a rail-to-rail input and output micro-power precision single supply operational amplifier with an enable feature. The device achieves rail-to-rail input and output operation and eliminates the concerns introduced by a conventional rail-to-rail I/O operational amplifier as discussed below. are tied together in parallel and a channel can be selected by pulling the EN pin to 0.8V or lower.The EN pin has an internal pull-down. If left open or floating, the EN pin will internally be pulled low, enabling the part by default.
Proper Layout Maximizes Performance
To achieve the maximum performance of the high input impedance and low offset voltage of the EL8176, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. The use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 49 shows how the guard ring should be configured and Figure 50 shows the top view of how a surface mount layout can be arranged. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. By setting the guard ring voltage equal to the voltage at the non-inverting input, parasitic capacitance is minimized as well. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators.
HIGH IMPEDANCE INPUT
IN 3 4 2 5 6 V+ EL8176 1
Rail-to-Rail Input
The input common-mode voltage range of the EL8176 goes from negative supply to positive supply without introducing offset errors or degrading performance associated with a conventional rail-to-rail input operational amplifier. Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The EL8176 achieves input rail-to-rail without sacrificing important precision specifications and without degrading distortion performance. The EL8176's input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. The input bias current versus the common-mode voltage range for the EL8176 gives us an undistorted behavior from typically 10mV above the negative rail all the way up to the positive rail.
Input Bias Current Compensation
The input bias currents as low as 500pA are achieved while maintaining an excellent bandwidth for a micro-power operational amplifier. Inside the EL8176 is an input bias canceling circuit. The input stage transistors are still biased with an adequate current for speed but the canceling circuit sinks most of the base current, leaving a small fraction as input bias current. The input bias current compensation/cancellation is stable from -40C to +125C and operates from typically 10mV to the positive supply rail.
FIGURE 49.
Rail-to-Rail Output
A pair of complementary MOSFET devices achieves rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The EL8176 with a 100k load will swing to within 3mV of the supply rails.
FIGURE 50.
Enable/Disable Feature
The EL8176, in the SOT-23 and SO packages, offers an EN pin. The active low EN pin disables the device when pulled up to at least 2.0V. When disabled, the output is in a high impedance state and the part consumes typically 3A. When disabled, the high impedance output allows multiple parts to be MUXed together. When configured as a MUX, the outputs
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FN7436.8 April 3, 2009
EL8176
Typical Applications
R4 100k R3 R2 K TYPE THERMOCOUPLE 10k 10k V+ + EL8176 V-
410V/C + 5V
R1 100k
FIGURE 51. THERMOCOUPLE AMPLIFIER
Thermocouples are the most popular temperature-sensing device because of their low cost, interchangeability, and ability to measure a wide range of temperatures. The EL8176 is used to convert the differential thermocouple voltage into single-ended signal with 10X gain. The EL8176's rail-to-rail input characteristic allows the thermocouple to be biased at ground and the converter to run from a single 5V supply.
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FN7436.8 April 3, 2009
EL8176 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
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FN7436.8 April 3, 2009
EL8176 SOT-23 Package Family
e1 A N 6 4
MDP0038
D
SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. F 2/07 NOTES:
E1 2 3
E
A2 b c
0.20 C
0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D
D E E1 e e1 L L1 N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only).
(L1)
H
6. SOT23-5 version has no center lead (shown as a dashed line).
A
GAUGE PLANE c L 0 +3 -0
0.25
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FN7436.8 April 3, 2009
EL8176 Wafer Level Chip Scale Package (WLCSP)
E
W3x2.6C
3x2 ARRAY 6 BALL WAFER LEVEL CHIP SCALE PACKAGE SYMBOL A MILLIMETERS 0.51 Min, 0.55 Max 0.225 0.015 0.305 0.013 0.323 0.025 0.955 0.020 0.50 BASIC 1.455 0.020 1.00 BASIC 0.50 BASIC 0.25 BASIC 0.00 BASIC Rev. 3 03/08 NOTES: 1. All dimensions are in millimeters.
D PIN 1 ID TOP VIEW
A1 A2 b D D1 E E1 e
A2
SD SE
A A1 b SIDE VIEW
E1 e SE SD 2
D1
1 b C B A
BOTTOM VIEW
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 18
FN7436.8 April 3, 2009

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